As integrated circuits (IC) have become smaller and more complex, IC designers depend on electronic design automation (EDA) software tools to facilitate the design of integrated circuits. Typically, the integrated circuit design process begins with a specification, which describes the functionality of the integrated circuit and may include a variety of performance requirements. Then, during a logic design phase, the logical implementation of the IC functionality is described using one of several hardware description languages such as Verilog or VHDL at the register transfer logic (RTL) level of abstraction. Typically, the EDA software tool synthesizes the abstract logic into a technology dependent netlist using a standard cell library from an IC manufacturer.
A standard cell is a group of transistors and interconnect structures that provides a Boolean logic function (e.g., AND, OR, XOR, XNOR, inverters) or a storage function (flipflop or latch). The simplest cells are direct representations of the elemental NAND, NOR, and XOR Boolean function, although cells of much greater complexity are commonly used (such as a 2-bit full-adder, or muxed D-input flipflop.) The cell's Boolean logic function is called its logical view: functional behavior is captured in the form of a truth table or Boolean algebra equation (for combinational logic), or a state transition table (for sequential logic).
A standard cell library includes hundreds or even thousands of standard cells, with which all logical representations may be implemented. The library includes various types of information about each of its standard cells, including its logic function, layout, power consumption, signal propagation delay, etc. These cells are realized as fixed-height, variable-width structures. The fixed-height enables them to be placed in rows, easing the process of automated digital layout. The library usually contains multiple implementations (cells) of the same logic function, differing in area and speed. Automated synthesis, place, and route (SPR) tools can then select the most efficient cell, based on the design requirements. The netlist is the standard cell representation of the IC design, at the logical view level. It consists of instances of the standard cells, and port connectivity between standard cells. Synthesis techniques ensure logical equivalency between the synthesized netlist and original RTL description.
After completion of the logic design phase, the IC undergoes a physical design phase, often referred to as place and route. Here, EDA software tools layout, or place, each cell in a floorplan. The result contains the physical location of each of the netlist's standard cells, but retains an abstract description of how the cell terminals are wired to each other. Each cell is assigned a unique (exclusive) location in the floorplan or the die map. A given cell is placed once, and may not occupy or overlap the location of any other cell. Then the physical components are connected, or routed, by adding interconnects between all of components that communicate with each other and with input/output pins outside of the IC according to the logic representation. In addition to signal connection lines, power supply lines and ground lines are also added at this time. At the end of the physical design phase, the representation of the semiconductor chip (in which the integrated circuit is implemented) is in the form of a Graphic Database System (GDS) or GDS II file.
Various verification processes such as Design Rule Check (DRC) and Layout Versus Schematic (LVS) are performed to verify the placed and routed IC can be manufactured and would work. DRC exhaustively compares the physical netlist and/or the GDS II file against a set of design rules from the IC manufacturer, then flags any observed violations for subsequent redesign. Examples include transistor spacing, metal layer thickness, and power density rules. The LVS process confirms that the layout has the same structure as the associated schematic; this is typically the final step in the layout process. The LVS tool takes as an input a schematic diagram and the extracted view from a layout. It then generates a netlist from each one and compares them. Nodes, ports, and device sizing are all compared. If they are the same, LVS passes and the design can continue.
While the current physical design process is able to implement all logic representations, improvements for optimizing the design to satisfy and/or maximize particular performance requirements continue to be sought.